The invention relates generally to memory interface circuits and more specifically to high speed multiple data-rate memory interface circuits.
Multiple data-rate interfaces, such as double data-rate interfaces, have become increasingly common. One such interface, the double data-rate (DDR) interface, communicates two bits of data per clock cycle at each data line. DDR interfaces are often used with high-speed memory devices, as well as other types of devices.
As DDR interfaces increase in speed, timing margins become smaller and more susceptible to error. For example, the accuracy in the timing between a clock signal and a data strobe signal (DQS) provided by a memory interface to a device such as a memory can be particularly important.
Typical DDR signals include DQS and data signals (DQ) provided by a transmitting device and received by a receiver, such as a memory. The receiver uses the DQS signals to retime and recover the DQ signals. For example, during write operations to a memory, the DQS signals may be center-aligned with the DQ data signals. In such a circuit, the receiving device samples and latches data from one or more DQ data signals on rising and falling edges of a DQS signal. Once in the memory device, the received data is then retimed from the DQS signal to an internal clock signal. The internal clock signal may be generated by a delay-locked loop that receives a clock signal from the transmitting device. Accordingly, for this internal retiming to properly occur, the timing between a DQS signal and a clock signal provided by a transmitting device should be well controlled.
In some DDR topologies, the clock signal provided by the transmitting device is provided to a number of memory devices in series, that is, to a first memory device, then a second, then a third, and so on. This topology is referred to as a “fly-by” topology and may also be used for control and address signals. This creates a skew, referred to as tDQSS, between the arrival time of a DQS signal and the clock signal at a memory device. Typically, this skew needs to remain below one-fourth of a clock cycle to avoid data reception problems in the memory device.
It is therefore desirable for a device and a memory interface to efficiently compensate for skew between clock and DQS signals provided to a memory device. It is also desirable to be able to compensate for a wide range of skew. It is further desirable for the device to be adaptable to the timing requirements of different interface standards with a high level of precision.